reg [7:0]data; initial begin     #10 clk =0;    forever #4 clk = ~clk; end initial begin     #20 rst=1;     #20 rst=0; endreg [7:0]data_sin[160000:0];  ////改动点数据矩阵长度设置integer i;    initial          begin              i=0;            begin              $readmemb("D:/Chapter_8/E8_1_QAMModem/QAM.txt",data_sin,0,160000); ///改动点数据矩阵长度  注意是“/”  而不是“\”            end              forever            begin                @(posedge clk)                    begin                        i <= i+1;                        din <= data_sin[i];                    end            end        end endmodule

matlab 写txt文本的代码

fid = fopen('data.txt','w');for oo=1:1:iif mod(oo,10) == 0fprintf(fid,'%f,%f,\n',sI1(oo),sQ1(oo));elsefprintf(fid,'%f,%f,',sI1(oo),sQ1(oo));endendfclose(fid);

　　

 

 

 

verilog 对应的写文件，写入IQ数据

integer file_out;initialbegin    file_out = $fopen("mI.txt");    if (!file_out) begin        $finish;    endend            wire signed [23:0] dout_s = fifo_fft_data[47:24];always @ (posedge clk) begin      if(fifo_fft_valid)    $fdisplay(file_out, "%d", dout_s);endinteger file_out_Q;initialbegin    file_out_Q = $fopen("mQ.txt");    if (!file_out_Q) begin        $finish;    endend            wire signed [23:0] dout_s_Q = fifo_fft_data[23:0];always @ (posedge clk) begin      if(fifo_fft_valid)    $fdisplay(file_out_Q, "%d", dout_s_Q);end

 

对应以上文件的matlab 读取数据：

　

%读取FPGA仿真出的数据clc;clear;close all;fid=fopen('mI.txt','r');[di,N]=fscanf(fid,'%lg',inf);fclose(fid);fid=fopen('mQ.txt','r');[dq,N]=fscanf(fid,'%lg',inf);fclose(fid);exp1=di+dq*1i;% exp2 = exp1(25000:30000);% exp2 = exp1(1024:8192);exp2 = exp1;plot(di);figure;plot(dq);figure;plot(20*log10(abs(fft((exp2).* window(@gausswin,length(exp2),4)))));